Analysis of the Distance Dependent Multiple Cell Upset Rates on 65-nm Redundant Latches by a PHITS-TCAD Simulation System
نویسندگان
چکیده
Recently, the soft error rates of integrated circuits is increased by process scaling. Soft error decreases the tolerance of VLSIs. Charge sharing and bipolar effect become dominant when a particle hit on latches and flip-flop. soft error makes circuit more sensitive to Multiple Cell Upset (MCU). We analyze the MCU tolerance of redundant latches in 65 nm process by device simulation and particle and heavy ion transfer code system (PHITS). The MCU rate of redundant latches is exponentially decreased by increasing the distance between redundant latches. These results coincide with the neutron experiments.
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